Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit

ABSTRACT

A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to a test circuit, a wafer having the testcircuit within a scribe line of the wafer. This invention also relatesto a method, using the test circuit, of monitoring of or conductingdefect analysis in a manufacturing process of semiconductor integratedcircuits.

2. Description of Related Art

To produce semiconductor integrated circuits, a manufacturing process(wafer process) processes semiconductor substrates (wafers). Themanufacturing process includes a large number of process steps. When thewafer process is completed, the wafer becomes a product wafer having aplurality of semiconductor integrated circuit chips (product chips)formed in respective chip areas on the wafer. The chips are, then,separated into individual dies at scribe lines between the chip areas.The dies are, then, packaged to become semiconductor integrated circuitproducts.

The chip areas are arranged on the wafer in rows and columns. Each ofthe scribe lines has a shape of a stripe having a constant width. Thescribe lines cross with each other to form a shape of a grid. The widthof the scribe line should be sufficient large so that the product chipscan be easily separated. At the same time, the scribe line should be asnarrow as possible to increase the number of product chips produced on awafer. Typically, the scribe line has the width of 100 to 150 μm.

Test circuits that allow easy and convenient measurement ofcharacteristics of various elements are also formed on the wafersimultaneously with the manufacturing of the product chips. When thewafer process is completed, the product chips are tested before theseparation to determine whether each of the product chips functions asrequired by the specification of the product. At this time, at leastsome of the test circuits formed on the wafer are also tested to measurethe characteristics of the elements and/or to analyze the cause offaults of the product chips.

The result of the test of the test circuit is used to monitor the stateof the manufacturing process. That is, for example, if abnormalcharacteristics are measured, the manufacturing process is checked todetermine the cause of the abnormality. The process is adjusted toprevent further occurrence of the abnormality. In addition, when anabnormality is found by the test of the product chips, for example, ayield of the product chips lower than a normal range is found, the testcircuits are extensively tested to determine the cause of theabnormality.

FIG. 7A is a circuit diagram illustrating a test circuit 100 of a firstconventional example. In the test circuit 100 shown, resistor elements102, such as contacts between source/drain regions and wires or viasbetween wires in different wiring layers, are connected in series. Theresistance value of the resistor elements 102, such as contacts or vias,is determined from the current flowing through the elements 102 and thepotential between pads 104 at both ends of the serially connectedresistor elements 102.

Such a configuration is generally referred to as a “contact chain” or“via chain”, and is most frequently used for monitoring manufacturingprocesses.

FIG. 7B is a circuit diagram illustrating a test circuit 110 of a secondconventional example. The test circuit 110 is used for a measuringmethod called a four-probes method in which four terminals 114, twoconnected to each end of one resistor element 112, are used. That is, acurrent is supplied to the resistor element 112 such as a contact or avia, and the potential difference between both ends of the element ismeasured. Thereby the resistance value can be measured accurately.

These test circuits 100 and 110 have a simplified circuit configurationand use a simplified test methodology, and also require a smaller numberof test pads for inputting/outputting signals to/from external measuringequipment. Thereby, the area of the test circuit can be reduced. Thetest circuit of these conventional examples, therefore, is often formedin the scribe line.

Such an arrangement can eliminate the need for forming the test circuitin the chip area, thereby saving the space available for the productchip. As a result, a number of product chips that can be produced perwafer is increased and the fabrication cost is minimized.

The test circuits of those conventional examples, however, have thefollowing drawbacks.

First, the test circuit 100 of the first conventional example shown inFIG. 5A includes a large number of resistor elements 102 (contacts orvias) arranged in the form of a chain. This arrangement increases thedetection sensitivity to an increase in the resistance values of theresistor elements 102 (contacts or vias) when the resistance values ofthe entire contacts or vias similarly increase.

When the resistance value of only one or a small number of the contacts(or vias) is increased, however, the resistance of the chain hardlyincreases unless the increase is significant relative to the resistanceof the entire chain. Therefore, it is often impossible to detect theincrease of the resistance of one or a small number of the contacts (orvias) in the chain.

For example, when the chain includes one hundred resistor elements 102,even if the resistance of one of the resistor elements 102 becomes tentimes the value of the other normal resistor elements 102, theresistance of the entire chain becomes merely 109% relative to thenormal case. Such increase in the resistance may be regarded as beingnormal. Thus, merely monitoring the resistance of the entire chaincannot provide a measurement that can be used to detect the abnormalityin one or a small number of the contacts (or vias). That is, this typeof test circuit has difficulty in detecting a defect in which, forexample, the resistance values of only a small fraction of contacts (orvias) are increased.

In fact, in a semiconductor integrated circuit manufacturing process,defects that present abnormalities in only a small fraction of thecontacts (or vias) frequently occur. In such cases, a decrease of theyield of the product chips occurs even when the chain resistance fallswithin a range that is determined to be normal. When the fraction ofcontacts or vias with the increased resistant is increased to such adegree that the resistance of the chain becomes abnormal, the yield ofthe chips is drastically reduced in many cases.

Such a tendency has become more pronounced as the minimum feature sizeof the semiconductor integrated circuit decreases. Accordingly, the testcircuit of the first conventional example cannot be satisfactory used inmonitoring a semiconductor integrated circuit manufacturing process.

On the other hand, the test circuit 110 of the second conventionalexample, as shown in FIG. 7B, is suitable to measure the resistance ofone resistor element 12, such as a contact (or via). However, itrequires four terminals 114 to measure the resistance value of oneresistor element 112 and thus requires the same number of pads. Eachtest pad is typically has a rectangular shape having a size of about 50to 100 μm on a side. Therefore, arranging only the four pads necessaryto measure the resistance of only one resistor element 112 requires alarge area.

Thus, for collecting an amount of measurement data sufficient toestablish a correlation with the yield of produced chips a large area isneeded to arrange a large number of test circuits 110. The test circuit110, therefore, cannot be realistically used in detecting defects, suchas an increase in the resistance of a small fraction of contacts (orvias).

Further, as will be explained in detail later, another test circuit isproposed in a paper presented at ICMTS (International Conference onMicroelectronic Test Structures), Vol.8, pp. 57, March 1995, which isincorporated herein by reference in its entirety. In this thirdconventional example, a large number of elements to be tested, such ascontacts, are arranged in the form of an array. Resistance values ofindividual elements can be measured and evaluated by using a counter, adecoder, and switches.

A similar test circuit is also disclosed in U.S. Pat. No. 4,719,411,which is incorporated herein by reference in its entirety.

However, the size of the third conventional example is large, and isimpossible to place in a scribe line on a wafer. Accordingly, the testcircuit cannot be placed in a chip area that is otherwise supposed to beallocated to place a product chip. Therefore, the third conventionalexample can not be suitably used for monitoring a semiconductormanufacturing process.

SUMMARY OF THE INVENTION

To overcome the foregoing problems of the related art, a first object ofthis invention is to provide a test circuit that may be advantageouslyutilized to monitor a manufacturing process. The test circuit allowsdetection of an abnormality in a fraction of a large number of elementsto be tested. The test circuit includes a pad used for testing theelements that has a dimension suitable to be placed within a scribe lineon a semiconductor wafer.

A second object of this invention is to provide a semiconductor productwafer having the test circuit.

A third object of this invention is to provide a method of monitoring amanufacturing process using the test circuit.

To achieve the first object, according to an aspect of this invention atest circuit is provided on a surface of a semiconductor wafer having aplurality of chip areas for placing semiconductor product chips andscribe lines between the chip areas. The test circuit comprises: aplurality of elements to be tested; a selection circuit thatsequentially selects at least one of the elements at a time; and aplurality of pads used for testing the elements. The test circuit andthe pads are placed within one of the scribe lines.

Similarly, according to another aspect of this invention a semiconductorproduct wafer is provided that comprises a plurality of product chipsplaced within respective chip areas arranged on a surface of thesemiconductor product wafer and a test circuit. The test circuitcomprises: a plurality of elements to be tested; a selection circuitthat sequentially selects at least one of the elements at a time; and aplurality of pads used for testing the elements. The test circuit andthe pads are placed within one of scribe lines that separate the chipareas.

Preferably, the plurality of pads comprise at least three pads arrangedalong a longitudinal direction of one of the scribe lines; and theplurality of elements are divided into at least two groups, eachincluding at least two elements. At least two of the groups of elementsare separately arranged in respective spaces between adjacent ones ofthe at least three pads.

Alternatively, the test circuit comprises: a plurality of elements to betested; and a shift register including a plurality of shift stages, eachfor selecting a predetermined number of the elements. Each of the shiftstages of the shift register and the predetermined number of theelements that can be selected by each of the shift stages are arrangedalong a direction generally perpendicular to a longitudinal direction ofone of the scribe lines to form a unit. The unit has a dimension thatcan be placed within one of the scribe lines. The test circuit includesat least one block, each comprising a plurality of the units arrangedalong the longitudinal direction of one of the scribe lines.

According to another aspect of this invention, a method of monitoring amanufacturing process for manufacturing semiconductor product wafers isprovided that comprises manufacturing semiconductor product wafers bythe manufacturing process. Each of the product wafers comprises: aplurality semiconductor product chips placed in respective chip areasarranged on a surface of the semiconductor product wafer; and a testcircuit placed within one of scribe lines between the chip areas. Thetest circuit comprises a plurality of elements to be tested and aselection circuit that sequentially selects at least one of the elementsat a time. The method of monitoring a manufacturing process furthercomprises: testing each of the elements in the test circuit in at leastone of the manufactured semiconductor product wafers; and evaluatingresults of the testing to monitor the manufacturing process.

Similarly, according to another aspect of this invention, a method ofmonitoring a manufacturing process for manufacturing semiconductorproduct wafers is provided that comprises manufacturing semiconductorproduct wafers including different types of semiconductor product wafersat an arbitrary ratio in an arbitrary order by the manufacturingprocess. Each of the different types of semiconductor product waferscomprises: a plurality of one of different types of product chips placedin respective chip areas arranged on a surface of the semiconductorproduct wafer; and a common test circuit placed within one of scribelines between the chip areas. The common test circuit comprises aplurality of elements to be tested and a selection circuit thatsequentially selects at least one of the elements at a time. The methodof monitoring a manufacturing process further comprises: selecting aplurality of the manufactured semiconductor product wafers comprising atleast two of the different types of the semiconductor product wafers;testing each of the elements in the test circuit in the selectedsemiconductor product wafers; and evaluating results of the testing tomonitor the manufacturing process.

Further, according to another aspect of this invention, a method ofmonitoring a manufacturing process for manufacturing semiconductorproduct wafers is provided that comprises manufacturing semiconductorproduct wafers, each including a plurality of product chips and a testcircuit. The test circuit comprises a plurality of elements to be testedand a selection circuit that sequentially selects at least one of theplurality of elements at a time. The method of monitoring amanufacturing process further comprises: testing each of the elements inthe test circuit in at least one of the manufactured semiconductorproduct wafers; evaluating results of the testing; and adjusting themanufacturing process according to the results of the evaluating toprevent occurrence of a decrease in a yield of the product chips.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a test circuit according to a firstembodiment of this invention for managing a fabrication process ofsemiconductor integrated circuits;

FIG. 2 is a layout schematically illustrating part of test circuitblocks and wiring blocks of the test circuit shown in FIG. 1;

FIGS. 3A and 3B are layouts schematically illustrating part of the testcircuit of the first embodiment, in which the test circuit blocks andthe wiring blocks, which have the layout pattern shown in FIG. 2, areprovided in a scribe line;

FIG. 3C illustrates the arrangement of the parts of the test circuitshown in FIGS. 3A and 3B in a test circuit according to the firstembodiment;

FIGS. 4A and 4B are graphs, respectively, showing the result obtained bymeasuring the resistance of individual contacts in a contact chainaccording to the test circuit of this invention;

FIG. 5 shows a circuit diagram of a test circuit including differentialamplifiers as the elements to be tested in a second embodiment accordingto the invention; and

FIG. 6 shows a circuit diagram of a test circuit including transistorsas the elements to be tested in a third embodiment according to theinvention;

FIGS. 7A and 7B are circuit diagrams of the first and the secondconventional test circuits, respectively; and

FIG. 8 is a circuit diagram of the third conventional test circuit.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

This invention was first described in Japanese Patent Application No.2001-107518, which is herein incorporated by reference in its entirety.

Before explaining the test circuit according to this invention,additional explanation of the third conventional explained will begiven.

FIG. 8 is a circuit diagram illustrating a test circuit 120 of a thirdconventional example. A large number of elements 122 to be tested, suchas contacts (or vias), are arranged in the form of an array (256columns×16 rows=4,096 four-terminal cross-contacts array), so thatresistance values of the individual elements 122 can be measured andevaluated.

In the test circuit 120, the elements 122, such as contacts (or vias),are connected such that a series chain is formed. When measuring theresistance of the elements 122, a current is first supplied between acurrent source Iin at one end of the chain and a current source lout atthe other end of the chain. The potential across both ends of eachelements 122 is then measured by connecting the both ends to a pair ofpotential difference measurement lines Vi and {overscore (Vi)} (i=1 to16) by switches (pass-transistors) 124. And the potential difference ismeasured, thereby allowing the measurement of the resistance of eachelement 122.

A (8-bit) binary counter and a (256-bit CMOS) decoder 126 connected tothe counter selectively activate one of gates G1 to G256 to measure theresistance of the contact (or via) of interest.

The test circuit 120 is primarily intended to evaluate the“distribution” of the resistance values of the elements 122.

According to the description in the ICMTS paper, arranging a chain ofone type of contacts (or vias) and the decoder for managing themeasurement of the contacts requires an area of 2.3 mm×0.3 mm. Inaddition, the test circuit 120 requires the arrangement of pads and thebinary counter (the decoder and the binary counter are collectivelyindicated at 126 in FIG. 8). Thus, it is impossible to arrange the testcircuit 120 within a scribe line, typically having a width of 100 μm to150 μm, on a semiconductor wafer. Accordingly, there is no other way butto arrange the test circuit by using areas that are otherwise supposedto be allocated to semiconductor integrated circuit product chips (chipsareas).

Similarly, the test circuit disclosed in U.S. Pat. No. 4,719,411includes a large number of elements connected in series. And theindividual elements are selected by a selection circuit to allow formeasurement of the characteristic of the individual elements. However,the test circuit is provided in a chip area that is otherwise used toplace a semiconductor integrated circuit product chip. Actually, thetest circuit does not have a size that can be placed within a scribeline.

Thus, neither the test circuit of the third conventional example or thetest circuit described in U.S. Pat. No. 4,719,411 is suitable as amonitor for managing a manufacturing process of semiconductor integratedcircuits.

Now, a test circuit suitable for monitoring a manufacturing process ofsemiconductor integrated circuits and a method for monitoring amanufacturing process of semiconductor integrated circuits according tothis invention will be described in detail in conjunction with anexemplary embodiment with reference to the accompanied drawings.

FIG. 1 is a circuit diagram illustrating the test circuit according to afirst embodiment of this invention. The test circuit may be used tomonitor, by way of example, a CMOS (Complementary Metal OxideSemiconductor) process as the manufacturing process.

The test circuit 10 for monitoring a manufacturing process ofsemiconductor integrated circuits includes a plurality (2n elements areshown) of elements 12 to be tested, which are contacts or vias,indicated by resistance symbols; a plurality of switches 11; and aselection circuit. Each switch 11 is constructed with a pair oftransmission gates 14 connected to the two ends of each element 12. Eachtransmission gate 14 is constructed with two pas-transistors, i.e., aPMOS transistor and an NMOS transistor. The selection circuit may be ashift register 16 having a plurality (n stages are shown) of shiftstages (16S1 to 16Sn), which controls the transmission gates 14 at thetwo ends of the elements 12 so as to sequentially select at least oneelement 12 at a time.

Viewed differently, two elements 12, two pairs of transmission gates 14,and one stage 16 sj of the selection circuit, which are verticallyarranged in FIG. 1, constitute one unit 30. A plurality (n) of the units30 is arranged in the horizontal direction in FIG. 1 to constitute thetest circuit 10.

In the test circuit 10 shown in FIG. 1, the elements 12 are connected inseries so as to form two rows of chains CHi (i=1, 2), in each of which nelements 12 are connected. The two ends of the chain CHi are connectedto a current source pad Ii (i=1, 2) and a current drain pad Iibar,respectively.

Two ends of each element 12 are connected to a pair of potentialmeasurement lines LVi and LVibar (i=1, 2) through the pair oftransmission gates 14. In other words, potential measurement lines LViand LVibar are provided commonly to a plurality (n) of elements 12 inthe chain CHi. One end of each potential measurement line LVi isconnected to a potential measurement pad Vi (i=1, 2), and one end ofeach potential measurement line LVibar is connected to a potentialmeasurement pad Vibar (i=1, 2), which constitutes a pair with thepotential measurement pad Vi.

Gates of the NMOS and PMOS transistors of the two transmission gates 14are connected to a pair of enable lines ENj and ENjbar (j=1 to n), whichextend from the corresponding stage 16Sj (j=1 to n) of the shiftregister 16. Each stage 16Sj (j=1 to n) of the shift register 16 isconnected in parallel to clock lines CK_A and CK_B, which is an invertedsignal of the CK_A. The clock line CK_A is directly connected to a clockinput pad CK_IN for inputting a clock signal, while the clock line CK_Bis connected to the clock input pad CK_IN through an inverter 18.

The shift register 16 is connected to a reset signal line RE leading toa reset signal pad RE_IN, so that each stage 16Sj of the shift register16 can be put into an initial state by a reset signal from the resetsignal line RE. As will be explained later, the clock signal and thereset signal are used as control signals to control the operation of theshift register 16.

In addition, in the test circuit 10, a power supply line and ground line(not shown) for the entire circuit are wired and are connected to apower supply pad Vdd and a ground pad GND, respectively.

In FIG. 1, by way of example, two chains CHi (i=1, 2) in which theelements 12, such as contacts or vias, are connected in series, areshown. In this case, different types of elements may be selected as theelements to be tested 12 for use in this invention. For example,contacts connected to N⁺ diffusion regions, contacts connected to P⁺diffusion regions, vias connected between metal wiring layers may beselected. Alternatively, the same type of contacts or vias fabricated indifferent sizes may also be selected.

While, in the illustrated embodiment, the elements 12 are connected toprovide two chains CH1 and CH2, they may be connected to provide onechain or three or more chains. The number n of the elements 12 connectedto form the chain is not particularly limited, but a relatively largenumber can be selected, ranging from about one hundred to severalhundreds, and/or about one hundred to two hundred.

When a direct current is supplied to the chain CHi (i=1, 2) in which theelements 12, such as contacts or vias, are connected in series, apotential difference is generated between both ends of each element 12.The potential difference is sent to the pair of potential measurementlines LVi and LVibar through the pair of transmission gates 14, and isexternally measured through the potential measurement pads Vi and Vibar.The resistance value of the element 12 is then calculated by dividingthe measured potential difference by the supplied direct current value.

That is, in the test circuit 10 shown in FIG. 1, Ii and Iibar pads areused as input pads to input an input signal to selected one of theelements. The Vi and Vibar pads are used as output paged to output anoutput signal from selected ones of elements.

In the illustrated embodiment, the potential measurement lines LVi andLVibar are commonly provided for all of the elements in each chain CHi.Therefore, the element 12 to be tested must be selected by one of thepairs of transmission gates 14. This selection is made as follows.

A clock signal input from the clock input pad CK_IN is used to generatetwo-phase clock signals of signal levels H (high) and L (low), whichcontrol the shift operation of the shift register 16.

At first, a reset signal is fed from a reset terminal to the shiftregister 16 so that only the leftmost stage 16S1 of the shift register16 is set to H (high) state, and the other stages are set to L(low)state. Thereby putting the shift register 16 into an initial state. Thatis, the leftmost stage 16S1 of the shift register 16 is in a state inwhich data has been input, i.e., the enable line ENj is H (high) and theenable line ENjbar is L (low). At this point, all of the other stagesare in a state in which no data is present, i.e., in a state in whichthe enable line ENj is L (low) and the enable line ENjbar is H (high).As a result, only the two pairs of transmission gates 14 arranged in theleftmost column in the FIG. 1 open.

Thereafter, each time the two-phase clock signal is input, data in theshift register 16 is shifted from the left stage, in the figure, to theright stages one by one. Thus, at a certain point, only two pairs oftransmission gates 14 in a corresponding column open, so that potentialsof both ends of two elements 12 are respectively sent on the potentialmeasurement lines LVi and LVibar, for each chain CHi. In such a manner,each of the elements 12 in each chain CHi is sequentially selected andthe resistance of the selected element is measured individually.

It is to be noted that this invention does not restrict the switches 11to the transmission gates 14. Any element that can disconnect or connectboth ends of the element 12 from or to the potential measurement linesLVi and LVibar may be used. That is, any kind of electricallycontrollable switch may be used.

In addition, the selection circuit is not limited to the shift register16, and thus any circuit that can select one of the measurement elements12 in each chain CHi (i=1, 2) may be used. Any selection circuit that isconventionally known can be used.

However, a shift register can be preferably used as the selectioncircuit. By using a shift register as the selection circuit, as shown inFIG. 1, a unit can be constructed with one or a predetermined number ofelements to be tested, switches, and a part of the selection circuit toselect the one or predetermined number of elements using the switches.That is, by using one of the stages 16 si of the shift register 16 asthe part of the selection circuit to select the elements in the unit,the same circuit configuration may be employed for each unit.

Additionally, the test circuit 10 of this invention may be provided withvarious elements and/or circuits that are necessary for the operation.

In essence, the test circuit of this invention is functionallyconfigured as described above.

In addition, the test circuit 10 according to this embodiment of thisinvention is characterized in that it is physically placed within ascribe line. That is, the test circuit 10 is placed on a semiconductorsubstrate on which a plurality of chip areas for placing semiconductorintegrated circuit chips and stripe-shaped scribe lines between the chipareas are formed. The test circuit 10 is placed within the scribe line.

FIG. 2 shows a physical layout of a part of the test circuit 10 shown inFIG. 1. The layout shown in FIG. 2 includes two test circuit blocks 40and a wiring block 42 arranged within a scribe line 20.

FIGS. 3A and 3B shows a physical layout of a part of the test circuit 10shown in FIG. 1. As shown by FIG. 3C, the right end of FIG. 3A isconnected to the left end of FIG. 3B. As shown in FIGS. 3A and 3B, aplurality of test circuit blocks 40 and wiring blocks 42 are arrangedwithin a scribe line 20 along a longitudinal direction of the scribeline 20.

In FIG. 2, circuit elements within the unit 30 shown in the circuitdiagram are arranged in one direction, in the same manner shown in thecircuit diagram of FIG. 1. That is, one stage 16Sj of the shift register16, two pairs of transmission gates 14, and two elements 12 to beselected by the stage 16Sj using the two pairs of transmission gates 14are arranged in a direction generally perpendicular to the longitudinaldirection (indicated by the arrow a) of a scribe line 20, i.e., in thevertical direction in FIG. 2, to form one unit 30. The physicaldimension of the unit 30 in the vertical direction is sufficiently smallsuch that the unit can be placed within the width of the scribe line 20.

In the illustrated test circuit 10, ten (10) units 30 are arranged inthe horizontal direction, i.e., in the longitudinal direction of thescribe line 20, to constitute one test circuit block 40.

The elements to be tested 12 such as contacts or vias in the units 30are interconnected by metal wires at the boundaries between adjacentunits 30 to constitute the contact or via chains (the chains CH1 andCH2). The chain serves as a current path for measuring a potentialbetween both ends of each element 12.

As shown in FIGS. 3A and 3B, a plurality of pads 38 are provided withinthe scribe line 20 at substantially regular intervals in thelongitudinal direction of the scribe line 20. A plurality of testcircuit blocks 40 configured in the manner described above are arrangedin the spaces between the test pads 38. That is, the circuit blocks 40and the test pads 38 are alternatively arranged linearly within thelongitudinal direction of the scribe line 20. Thus, the test circuitblocks 40 are advantageously arranged between the pads 38 to reduce thearea of the entire test circuit 10 including the pads 38.

Additionally, the test circuit blocks 40 may also be arranged outside ofthe test pads 38, i.e., on the right of the right-most pad and/or on theleft of the left-most pad in the column in which the test pads 38 arearranged in the longitudinal direction.

It may be possible to arrange all the units 30 in one block 40 dependingon the number of required units. If, however, all the units 30 cannot bearranged in a space between two adjacent test pads 38, the units 30 canbe arranged in a plurality of blocks 40. That is, the number of units 30that fit between the adjacent test pads 38 are arranged in each testcircuit block 40.

To facilitate probing with probes and for ease of design, the test pads38 are arranged with the same interval. That is, spaces between the pads38 are set to be substantially the same. However, the spaces can also beset to be differently.

The potential measurement lines LVi and LVibar that are provided foreach element 12 in the circuit block 40 linearly extend across the pad38 in the longitudinal direction within the scribe line 20. Similarly,current feed lines Lli (by which the elements 12 are connected in seriesto form the chain CHi) that serve as current paths, power supply linesLVdd, and ground line LGND are linearly arranged across the pads 38 inthe longitudinal direction within the scribe line 20. These wiring linesrun beneath the pads 38 that do not have to be connected to, and areconnected through vias to the pads that need to be connected.

Thereby, a wiring block 42 including a pad 38 and wiring lines runningacross the pad 38 is formed. As shown in FIGS. 3A and 3B, in the testcircuit 10, a plurality of test circuit blocks 40 (in the illustratedexample, four test circuit blocks are shown) is connected via wiringblocks 42. As shown in FIG. 2, these wiring blocks 42 are fitted withinthe width of the scribe line 20.

Thus, the elements 12 to be tested (e.g., contacts or vias), theswitches 11 (e.g., the pair of transmission gates 14), and a part of theselection circuit (e.g., a stage 16 si of a shift register 16) arearranged as a unit 30 in a first direction (the vertical direction). Aplurality of such units 30 is arranged in a second direction (thehorizontal direction), which is generally perpendicular to the firstdirection, to provide a test circuit block 40. The test circuit block 40has an appropriate size that can be fitted within the space between thetest pads 38. A plurality of test circuit blocks 40 are arrangedalternately with the wiring blocks 42 in the second direction within thescribe line 20.

This arrangement can provide a test circuit 10 including test pads 38physically elongated in the second direction and can be fitted within anelongated scribe line 20. This configuration of the units 30 and testcircuit blocks 40 facilitates quick adjustment of the number of elements12 in each chain (the number of stages of the chain CHi) as required.

While not shown in the circuit diagram of FIG. 1, various elements thatare required for testing the test circuit 10 can also be configured asblocks 44 and 46 (see FIG. 3A) so as to be fitted within the scribe line20.

The test circuit according to the embodiment of this invention isessentially configured as described above. Measuring the resistancevalues of the elements 12 in the chain CHi using the test circuit 10shown in FIGS. 1, 2, 3A, and 3B makes it possible to detect defects orabnormalities, such as an increase in resistance, that occurs in a smallfraction of the elements 12.

FIGS. 4A and 4B show the results of measuring of the contact resistanceof each contact in the chain CHi (i=1, 2) of the test circuit 10. Inthis example, the test circuit 10 was fabricated so as to include twotypes of contacts, i.e., 104 contacts to N⁺ diffusion regions and 104contacts to P⁺ diffusion regions. Each contact has a size of 0.4 μm. Thetest circuit 10, thus fabricated, in this example, has a size of 98μm×2,400 μm, and was fitted within the scribe line 20 having a width of100 μm.

FIGS. 4A and 4B show the test results for the contacts to the N⁺diffusion regions and to the P⁺ diffusion regions, respectively. Thenumbers on the horizontal axes in FIGS. 4A and 4B indicate the stage inthe contact chain, and the vertical axes indicate the contact resistancevalues (Ω).

As shown in FIGS. 4A and 4B, most of the contacts in each chain havesubstantially the same resistance within a normal range of variation.However, one of the contacts in each chain has a significantly higherresistance compared with other contacts. Thus, the test circuit 10 ofthis invention can be used to detect a defect even in the case in whichan increase in resistance occurs only in a small fraction of thecontacts while the majority of them are normal.

The detection of such a defect or an abnormality makes it possible toissue an alarm prior to an occurrence of an actual product defect in amanufacturing process. When the alarm is issued, it is possible toexamine and adjust the manufacturing process to prevent the actualoccurrence of the defect in the manufactured semiconductor integratedcircuit product chips. That is, the manufacturing process can beeffectively monitored by providing the test circuit 10 in the scribeline of the product wafers and by testing the test circuit 10 when thewafer process is completed. Thereby, the occurrence of defects thatcause a low yield of the product chips can be prevented.

Alternatively, the test circuit 10 can be provided in the scribe lineand tested at the time of occurrence of a defect causing a decrease inyield of the product chips. Testing the test circuit 10 facilitates theidentification of a defective point, and the cause of the defect in themanufacturing process can be made clear.

That is, as shown in FIGS. 4A and 4B, the defective element having anabnormal characteristic can be electrically identified. And the physicallocation of the defective element can be easily identified, because theelements 12 are physically arranged in a plurality of block groups 40 inthe longitudinal direction in the scribe line 20. The identified elementcan be closely analyzed by, for example, SEM (scanning electronmicroscope) or TEM (transmission electron microscope).

In the method for monitoring a manufacturing process of semiconductorintegrated circuits according to this invention, semiconductorintegrated circuit chips are formed in a plurality of chip areas on thesurface of a semiconductor wafer. The test circuit 10 is simultaneouslyformed in the scribe line 20 between the chip areas. The test circuit 10is tested when, for example, the wafer process is completed.

In the testing of the test circuit 10, the shift register 16sequentially selects one or more of the elements 12, such as contacts orvias, in the chain at a time, and characteristics of the elements 12,such as resistance values of the contacts or vias, are measured. Thus,by analyzing the results of the testing, an occurrence of anabnormality, such as an increase in resistance in a small fraction ofthe elements 12 can be detected.

Therefore, the production process can be continuously monitored andabnormalities of the production process can be detected before anoccurrence of the defect, or low yield of the actual semiconductorintegrated circuit product chips, manufactured by the manufacturingprocess.

An operator can make the determination as to whether the test circuithas an abnormality. Alternatively, according to this embodiment, a testsystem (configured with a prober, tester, controlling computer, and soon) can automatically issue a warning. That is, a reference value and apermissible range are set in the test system and the system issues thewarning when a test result that exceeds the permissible range isobtained.

The warning can be displayed on a display screen to help the operatormake a decision. Further, the warning can be automatically added to therecord of the test result. Alternatively, the warning may beautomatically transmitted, for example, in the form of an electronicmail, to an operation manager.

In addition, a specific process step that could be a cause for theabnormality may be set depending on the type of the test circuit and themode of the abnormality and can be stored in the system in advance. Upondetection of an abnormality, the test system may automatically issue awarning to request that the operation manager check and adjust thespecific process step. The system may also automatically terminate theoperation of the specific process.

Alternatively, the permissible range may be set into two stages. When afirst-phase permissible range is exceeded, a warning is issued to theoperation manager. When a second-phase permissible range is exceeded,the set process is automatically terminated.

Even when the measurement result obtained falls within a range in whichan immediate measure is not needed, the result could be stored in thetest system or in a system managing the manufacturing process. With thisarrangement, a report indicating the trend of test results can becreated in response to a request by the operation manager orautomatically at regular intervals. The report can be sent from the testsystem (or from the process management system) to the operation managerto ask whether the state of the process needs to be checked or not.

As explained above, by providing the test circuit 10 on the productwafers and by testing the test circuit 10, it is possible to detectabnormalities that occur in a small fraction of the elements. Thereby, awarning can be issued before a decrease in the production yield becomesmanifest. The test result can additionally be used to adjust theproduction process.

The test circuit 10 according to this invention may also beadvantageously used in monitoring a so-called “flexible manufacturing”facility in which multiple types of semiconductor integrated circuitproducts are manufactured with varying ratios and sequences depending onthe demand of the product.

The types of the products may include products in different categories,such as memory, logic and analog semiconductor integrated circuitproducts. The types of the products may also include products in thesame category with different specifications. For example, when themanufacturing process is used to manufacture ASIC (Application SpecificIntegrated Circuit) products, the types of products mainly include logicproducts with different specifications.

The flexible manufacturing facility manufactures various types ofsemiconductor product wafers having respective types of semiconductorintegrated circuit product chips in their chip areas. Sizes of the chipareas in these product wafers vary depending on the types of thesemiconductor integrated circuit products.

However, all of the types of semiconductor product wafers have scribelines between the chip areas and the widths of the scribe lines can bemade the same or substantially the same. Therefore, the same testcircuits 10 can be commonly placed within the scribe lines 20 of all orat least some of the types of semiconductor product wafers.

This arrangement enables sequential and coherent gathering of test dataand monitoring of the manufacturing process even when the types ofproducts to be manufactured vary. For example, even when a specific typeof product is not manufactured for a certain period, the same testcircuits provided in scribe lines 20 on different type of semiconductorproduct wafers can be tested to monitor the manufacturing process.

Thus, the feature of the test circuit 10 of this invention, i.e., thecapability of detecting abnormalities in individual elements 12 among alarge number of elements 12, is utilized to detect an abnormality in theflexible manufacturing process at an early stage. That is, theabnormality in the elements 12 in the test circuit can be detectedbefore a decrease in the yield of one or some of the types of productchips occur.

Different types of defects may have a different influence on the yieldof different types of product chips. When a manufacturing process ismainly used to manufacture a first type of product chip that is notstrongly influenced by a type of defect, an average yield of the productchip may be kept high even if a density of that type of defect becomeshigh. Therefore, the operation manager may not recognize the necessityof adjusting the manufacturing process. If the same manufacturingprocess with the high density of the type of defect is used tomanufacture a second type of product chip that is strongly influenced bythe type of defect, however, the yield of the second type of productchip likely to be very low.

On the other hand, if test circuits that are sensitive to that type ofdefect are provided on the product wafers for forming a first type ofproduct chip, the increase of the defect would be detected. Then, themanager could recognize the necessity of the adjustment even beforestarting the manufacturing of the second type of product. Thus,occurrence of a low yield of the second type of product chip could beprevented.

The test circuit 10 of the present invention can also advantageously beused to monitor a manufacturing process used to manufacture varioustypes of semiconductor product wafers at an arbitrary ratio in anarbitrary order.

In this case, at least two types of the product wafers having the commontest circuit 10 in their scribe lines 20 are selected from the varioustypes of product wafers. The test circuits 10 in the selected productwafers are tested to detect an abnormality in the elements 12 in thecommon test circuits 10. Thus, even when the various types ofsemiconductor integrated circuit product chips are manufactured at anarbitrary ratio and in an arbitrary order, an abnormality in themanufacturing process can be detected at an early stage.

The semiconductor product wafers to be tested may be selected such thatintervals between the times of manufacture of the wafers aresubstantially the same. Thereby, the state of the manufacturing processis constantly monitored with substantially the same interval using thecommon test circuit 10 even when the types of the products manufacturedby the process vary arbitrary.

In the manufacturing of semiconductor integrated circuits, a pluralityof wafers are grouped into a lot and processed together. Usually, thesame type of semiconductor integrate circuit chips are formed using thesame mask in each of the chip areas on each of the wafers in the lot.Thereby, a large number of the same type of semiconductor integratedcircuit product chips are produced simultaneously.

Therefore, the selection of the at least two types of product wafersactually selects at least two lots of the wafers. One or some of thewafers in the selected lots are further selected and the test circuits10 on the selected wafers are tested. Usually, the test circuit 10 isformed in the scribe line simultaneously with the product chip in thechip area using a common reticle having mask patterns for both theproduct chip and the test circuit 10. Therefore, a large number of testcircuits 10 are formed on each product wafer.

It is not necessary to test all of the test circuits 10 formed on theselected product wafer. Only some of the test circuits in predeterminedpositions (e.g., center, top, bottom, right, left) on the wafer can betested.

Recently, a foundry service is widely used in which upon receipt oforders from various clients, semiconductor integrated circuit productchips are manufactured for respective clients. In the foundry service,the chip areas on the semiconductor wafer are allocated for the clients.That is, the manufacturer manufactures semiconductor product chips forthe client in the chip areas on the wafers using the mask data providedby the client. Therefore, the manufacturer cannot utilize the chip areasto form test circuits for monitoring the manufacturing process.

Even in this case, according to this invention, the manufacturer canprovide the common test circuit, designed or selected by themanufacturer, in scribe lines of the wafers. The manufacturer canutilize the test circuit to monitor the manufacturing process.

The client may also utilize the test circuit provided by themanufacturer. That is, the client may monitor the state of themanufacturing process of the manufacturer by testing the test circuit.The client may request the manufacture to check or adjust the processwhen an abnormal test result is obtained.

Further, the client may also request the manufacturer to provide a testcircuit selected by the client on the wafer manufactured for the client.When utilizing multiple manufacturers, the client may gather consistentmonitoring data about the states of the process of the multiplemanufacturers by requesting the manufactures to provide common testcircuits on the product wafers.

As explained above, the test data may be stored in the test system or inthe manufacturing management system.

When an abnormal test result is obtained, or when a decrease in a yieldof a certain type of product chips occurs, the test results obtainedfrom the common test circuit on the previously manufactured productwafers stored in the test system or in the management system can beanalyzed in detail. Even when the low yield occurs in a product that wasnot manufactured for a certain period, a coherent analysis can be made.That is, the analysis can be made using the stored test resultsincluding those obtained from the common test circuits formed ondifferent types of product wafers during the period when the productchips with the low yield was not manufactured.

Further, when the abnormality occur in one type of product, detailedanalysis using, for example, SEM and TEM, can also be made on the commontest circuits on the other types of product wafers. Such analyses usingthe common test circuit are highly effective to specify the cause of theabnormality.

As explained above, the test circuit 10 according to this invention mayadvantageously be used for monitoring a manufacturing process used formanufacturing multiple types of semiconductor product wafers. The testcircuit 10 according to this invention may also advantageously be usedfor analyzing the cause of an abnormality in the manufacturing processused for manufacturing multiple types of semiconductor product wafers.

The test circuit 10 can be provided with varying sizes or types of theelements 12, such as contacts or vias. Analysis of such test circuit 10enables identification of a defective point, and further clarifies thecause of the defect in the manufacturing process.

The above description focuses on the case in which the test circuit 10is provided in a scribe line 20. However, the detection of anabnormality occurring in a fraction of the elements 12 of the testcircuit 10 that can be equally achieved in a case in which the testcircuit is provided in a chip area.

By detecting the abnormality in the fraction of the elements 12, themanufacturing can be adjusted to correct the abnormality. Thereby,occurrence of an abnormality in the actual product chips can beprevented and a stable operation of the manufacturing process can beachieved.

In this case, it is possible to use the test circuit 10 having theconfiguration and layout as shown in FIGS. 1, 2, 3A, and 3B. That is,one or a certain number of elements 12 to be tested, switches 11, andthe part of the selection circuit to select the elements 12 using theswitches 11 are arranged in the first direction to form one unit 30. Aplurality of the units 30 is arranged in the second direction generallyperpendicular to the first direction to form one block 40 having anappropriate size. A plurality of the blocks 40 are is alternatelyarranged with the test pads 38 in the second direction to constitute theelongated test circuit 10. This arrangement is advantageous to reducethe area required to place the test circuit 10 including the pads 38.

The test circuit 10 and method of monitoring a manufacturing process ofsemiconductor integrated circuits have been described in detail inconjunction with various aspects of this invention. However, thisinvention is not limited to those specific aspects described. Variousimprovements or design changes may naturally be made thereto withoutdeparting from the scope or spirit of this invention.

In the test circuit 10 shown in FIG. 1, a plurality of elements 12 to betested is connected in series to form a chain. It is also possible toconstruct a test circuit by connecting a plurality of elements to betested in parallel such as shown in U.S. Pat. No. 5,485,095, which ishereby incorporated by reference in its entirety.

In the test circuit 10 shown in FIG. 1, resistor elements such ascontacts or vias are used as the elements to be tested. Various elementsother than contacts and vias, however, may be also used as the elementsto be tested in the test circuit.

For example, a memory such as SRAM including a plurality of memorycells, as elements to be tested, and row- and column decoders as aselection circuit to sequentially select each of the memory cells, maybe used as a test circuit. When the design rule of the manufacturingprocess is small enough, it is possible to place in a scribe line amemory with a number of memory cells sufficient to detect defects thatoccur in a small fraction of the memory cells.

For example, using a 0.18 μm design rule manufacturing process, an SRAMhaving about 1 K bits memory cells including the selection circuit andswitches may be easily placed within a scribe line. That is, by dividingthe 1 K bits SRAM into two blocks, each of the blocks can be placedbetween two adjacent pads with a space of 60 μm between them within ascribe line having a width of 100 μm. The selection circuit and switchesto select each of the cells within each block can also be placed betweenthe adjacent pads within the scribe line.

Further, by dividing the memory into more than two blocks, or by using asmaller design rule manufacturing process, a memory having more than 1 Kbits cells may be placed within a scribe line. It is also possible toplace, for example, a test pattern generation circuit such as shown inU.S. Pat. No. 5,485,095, which is hereby incorporated by reference inits entirety, within the scribe line.

It is possible to make the test circuit highly sensitive to certaintypes of defects by, for example, intentionally shifting an alignmentbetween certain layers, making a dimension of a certain portion in thememory cell smaller than the standard size, and so on.

When the semiconductor product chip or at least some of the differenttypes of the semiconductor product chips include an analogy circuit, aprecise matching of transistor characteristics are higher required toachieve a high yield in the product chip. The matching of transistorcharacteristics may be evaluated by, for example, evaluatingcharacteristics of analog amplifiers such as differential amplifies.

FIG. 5 shows a circuit diagram illustrating the test circuit accordingto a second embodiment of this invention including differentialamplifiers as elements to be tested.

The test circuit 50 shown in FIG. 5 includes n differential amplifiers60 as elements to be tested In the test circuit 50, similar to the testcircuit 10 shown in FIG. 1, each of the elements to be tested (adifferential amplifier 60), switches (transmission gates 72 and 74), anda part of a selection circuit (a shift stage 16 sj of a shift register)that selects the elements using the switch forms a unit 70.

Each of the differential amplifiers 60 includes a pair of NMOStransistors 62. Sources of the NMOS transistors 62 are coupled andconnected to the drain of another NMOS transistor 65. The source of theNMOS transistor 65 is connected to GND. Gates of the pair of NMOStransistors 62 forms input terminals of the differential amplifier 60.Drains of the NMOS transistors 62 are connected to drains of respectiveone of a pair of PMOS transistors 64. Sources of the pair of PMOStransistors 64 are connected to Vdd. Gates of the pair of PMOStransistors 64 are coupled and connected to the drain of one of the pairof NMOS transistors 62, thereby the pair of PMOS transistors 64 operatesas a current mirror.

The drain of another one of the pair of NMOS transistors 62 is connectedto the gate of PMOS transistor 66. The source of the PMOS transistor 66is connected to Vdd. The drain of the PMOS transistor 66 is connected tothe drain of an NMOS transistor 67 to form an output terminal of thedifferential amplifier 60. The source of the NMOS transistor 67 isconnected to GND.

An input voltage is input as an input signal from an voltage input padVin, and is supplied to both of the input terminals of each of thedifferential amplifiers 60.

One of the transmission gates 72 in each unit 70 of the test circuit 50supplies, when the unit is selected by the shift stage 16 sj, biasvoltage to gates of NMOS transistors 65 and 67 in the unit. The biasvoltage is input from a bias voltage input pad Vbi. Thereby, thedifferential amplifier 60 in the selected unit 70, which is a selectedelement to be tested, operates. Because the common input voltage issupplied to the both of the input terminals of the differentialamplifier 60, the output voltage output from the drain of the PMOStransistor 66 indicates a degree of matching of the pair of NMOStransistors 62.

Another transmission gate 74 in each unit 70 transmits the outputvoltage of the differential amplifier, as an output signal of the testcircuit 50, to an output pad Vout. Thereby, the degree of matching ofthe pair of NMOS transistors 62 in each of the differential amplifiers60 can be evaluated by sequentially selecting one of the units 70 andmeasuring the output voltage output from the output pad Vout.

The matching of transistor characteristics may also be evaluated bydirectly measuring each of transistors selected from a plurality oftransistors by using a test circuit such as shown in FIG. 6.

FIG. 6 shows a circuit diagram illustrating the test circuit 80according to a third embodiment of this invention including a pluralityof transistors 92 as elements to be tested. In the test circuit 80 shownin FIG. 6, the plurality of NMOS transistors 92 are connected inparallel between a power supply line LVdd and a ground line LGND. Thepower supply line LVdd is connected to a power supply pad Vdd, and theground line LGND is connected to a ground pad GND. The power supply padVdd is also used as a current measurement pad Imes. That is, the currentflows into the Vdd (Imes) pad is measured as an output signal of thetest circuit 80.

Similar to the test circuits 10 and 50, the test circuit 80 is organizedin a plurality of units 90 each including one of the NMOS transistors 92as an element to be tested, a switch (a transmission gate 96) and a partof a selection circuit (shift stage 16 sj of a shift resistor 16) thatselects the NMOS transistor using the switch. Each of the units alsoincludes a resister 94 connected between the gate of the NMOS transistor92 and the ground line LGND.

An input voltage is input as an input signal to an input voltage padVin, and the transmission gate 96 in the selected one of the units 90supplies the input voltage to the gate of the NMOS transistor 92 in theunits 90. Thereby, the selected one of the NMOS transistors 92 becomesON. While the other NMOS transistors 92 are OFF because the resistors 94keep the gates of the other NMOS transistors at the GND potential.Therefore, the drain current of the selected one of the NMOS transistors92 flows into the Vdd (Imes) pad.

By sequentially selecting one of the plurality of transistors 92 at atime by the shift resistor 16, and by measuring the drain current ofselected one of the transistors 92, a distribution of drain current at afixed gate voltage can be evaluated. Thereby matching of the transistorcharacteristics can be evaluated.

The test circuits 50 and 80 may also be physically arranged in a scribeline similar to the case of the test circuit 10. That is, the element tobe tested, the switch(es) and the part of the selection circuit in eachunit are arranged in the first direction. A plurality of units isarranged in the second direction generally perpendicular to the firstdirection to form one circuit block having an appropriate size. And aplurality of the circuit blocks is alternately arranged with the pads inthe second direction to construct an elongated test circuit that fit tothe scribe line. Thereby, test circuits 50 and 80 including one hundredor more elements to be tested (differential amplifiers of transistors)can be placed within a scribe line having a width of, for example, 100μm.

As described above, the test circuit according to this invention enablesdetection of an abnormality that occurs in a fraction of elements to betested. Therefore, the test circuit may detect the abnormality before adecrease in a yield of the product chips occurs. Further, the testcircuit can be placed within a scribe line between chip areas.Therefore, the test circuit does not waste the region that is intendedto be allocated to product chips. As a result, the test circuit can beused to monitor a manufacturing process.

In the method of monitoring a manufacturing process according to thisinvention, it is possible to issue a warning before a decrease in ayield of product chips becomes manifest. Particularly, in a flexiblemanufacturing or foundry service, providing the same test circuitcommonly on different types of semiconductor product wafers formanufacturing different types of product chips allows sequential andcoherent monitoring of the manufacturing process.

In addition, the test circuit according to this invention is alsoadvantageously used to identify a cause of a defect or abnormality whena low yield occurs in the product chips.

1. A method of monitoring a manufacturing process for manufacturingsemiconductor product wafers, comprising: manufacturing semiconductorproduct wafers by the manufacturing process, each of the product waferscomprising: a plurality of semiconductor product chips placed inrespective chip areas arranged on a surface of the semiconductor productwafer; and a test circuit placed within one of scribe lines between thechip areas, the test circuit comprising a plurality of elements to betested and a selection circuit that sequentially selects at least one ofthe elements at time; testing each of the elements in the test circuitin at least one of the manufactured semiconductor product wafers; andevaluating results of the testing to monitor the manufacturing process.2. The method according to claim 1, wherein a number of the elementsincluded in the test circuit are sufficiently large to detect a changeof a state of the manufacturing process before a decrease of a yield ofthe semiconductor product chip occurs.
 3. A method of monitoring amanufacturing process for manufacturing semiconductor product wafer,comprising: manufacturing semiconductor product wafers includingdifferent types of semiconductor product wafers at an arbitrary ratio inan arbitrary order by the manufacturing process, each of the differenttypes of semiconductor product wafers comprising: a plurality of one ofdifferent types of product chips placed in respective chip areasarranged on a surface of the semicondcutor product wafer; and a commontest circuit placed within one of scribe lines between the chip areas,the common test circuit comprising a plurality of elements to be testedand a selection circuit that sequentially selects at least one of theelements at a time; selecting a plurality of the manufacturedsemiconductor product wafers comprising at least two of the differenttypes of the semiconductor product wafers; testing each of the elementsin the test circuit in the selected semiconductor product wafers; andevaluating results of the testing to monitor the manufacturing process.4. The method according to claim 3, wherein a number of elementsincluded in the test circuit are sufficiently large to detect a changeof a state of the manufacturing process before a decrease in a yield ofthe different types of product chips occurs.
 5. The method according toclaim 3, wherein the evaluating step is performed when a decrease in ayield of at least one of the different types of product chips occurs. 6.The method according to claim 3, further comprising: adjusting themanufacturing process according to a result of the evaluating to preventoccurrence of a decrease in a yield of at least one of the differenttypes of product chips.
 7. The method according to claim 3, wherein theplurality of manufactured semiconductor product wafers are selected suchthat the selected semiconductor product wafers are manufactured withapproximately a fixed interval.
 8. The method according to claim 3,wherein different customers provide mask patterns used to manufacturethe different types of product chips.
 9. A method of monitoring amanufacturing process for manufacturing semiconductor product wafers,comprising: manufacturing semiconductor product wafers, each including aplurality of product chips and a test circuit comprising a plurality ofelements to be tested and a selection circuit that sequentially selectsat least one of the plurality of elements at a time; testing each of theelements in the test circuit in at least one of the manufacturedsemiconductor product wafers; evaluating results of the testing; andadjusting the manufacturing process according to the results of theevaluating to prevent occurrence of a decrease in a yield of the productchips.
 10. The method according to claim 9, wherein a number of theelements included in the test circuit are sufficiently large to detect achange of a state of the manufacturing process before the decrease inthe yield of the product chip occurs.